June 16-20, 2013

Leipzig, Germany

Dr. Chris Newburn

Performance & Feature Architect, Xeon Phi™ Product Family, Intel

Chris (CJ) Newburn serves as a performance and feature architect for the Intel' Xeon Phi product family. He has contributed to a combination of hardware and software technologies that span co-processor hardware, compiler optimization, tools and performance analysis features, ISA changes, microarchitecture, microcode middleware, and JVM/JIT/GC optimization over the last fifteen years. Performance analysis and tuning has figured prominently in the development and production readiness work that he's done.
He has submitted nearly twenty patents and has numerous journal and conference publications. He has served as program chair for CGO, a premier back-end compiler conference, on several program committees, as a journal editor, and as an NSF panelist. He wrote a binary-optimizing, multi-grained parallelizing compiler as part of his Ph.D. at Carnegie Mellon University. Before grad school, in the 80s, he did stints in a couple of start-ups, working on a voice recognizer and a VLIW mini-super computer. He's glad to have worked on volume products that his Mom uses.

Speaker at: Research Paper Session 09
Offload Compiler Runtime for the Intel® Xeon Phi™ Coprocessor
Program may be subject to changes.